This invention relates to digital computers, and more particularly to a subtracting circuit using a two's complement sum.
When subtracting, in two's complement notation, it is common practice to use arithmetic logic units (ALU's), as an example, the Fairchild 9340. Because an n-bit input can result in an n + 1 bit output, it is necessary to expand the sign bits of the inputs to two bits each. Since the arithmetic logic unit normally is a four bit device, a substantial efficiency loss occurs when the application requires expanding the sign bit such that the 4n + 1 bits are required (n = 1, 2, 3,). This inefficiency results in larger physical package size, higher power dissipation, and in some cases, higher cost.
The invention employs a one bit full adder with a complement sum output to provide an efficient implementation of subtraction of two 4n bit numbers. Signal processing, computing and special purpose processing functions frequently employ 4n bit lengths, and most complex arithmetic elements are sized for multiples of 4 bits. There exists, therefore, a wide range of potential applications for this subtracting system.